1. Technical Field
This invention relates to a technique allowing a distributed sample scrambler used in a cell-based physical layer of ISDN(Integrated Service Digital Network) to be employed in a 16-bit mode utopia interface, more particularly, to a parallel processor of a distributed sample scrambler, without an extra logic, capable of parallel-processing a pseudo random binary bit stream based on a predetermined bit unit according to a mode selection signal.
2. Description of the Related Arts
In a prior art, a parallel processor of distributed sample scrambler can process an 8-bit mode cell of the utopia interface located between an ATM(asynchronous transmission mode layer) and a physical layer of the ISDN, however, it can""t process 16-bit mode cell which have a different format of the 8-bit mode cell.
Table 1 shows a 16-bit mode cell format of the utopia interface.
One byte is added to a UDF (User-Defined field) nearly located in a head error control (HEC) signal and, therefore, totally 54 byte cells are transmitted between the ATM layer and the physical layer.
In the prior art, therefore, in case that the distributed sample scramble is processed in the 16 bits, one byte PRBs is generated on UDF passing time, so one byte PRBs should be shifted to be added proper position in the ATM cell. But this shift method cannot solve the problem because one byte is left at each ATM cell.
It is, therefore, an primary object of the present invention to provide a parallel processor of a distributed sample scrambler, which utilizes a simple logic to parallel-process a predetermined bit of the pseudo random binary bit stream, so that easily and reliably discriminate the cell boundary of the IDSN.
According to the present invention, a parallel processor of a distributed sample scrambler, comprises: first pseudo random bit stream production means for producing a first pseudo random binary bit stream within a word parallel clock according to a predetermined byte of-an ATM (Asynchronous Transfer Mode) cell applied from an external; second pseudo random bit stream production means for producing a second pseudo random binary bit stream within a word parallel clock according to the predetermined byte of the ATM cell; a selection means for selectively producing one of the first and the second pseudo random binary bit streams according to an external signal; storing means for temporally storing an output signal from the selection means to produce the temporally stored output signal to both the first pseudo random binary bit stream production means and the second pseudo random binary bit stream production means; exclusive-OR means for processing an exclusive-OR operation with two inputs, wherein, one input is an output signal from the storing means and the other input is the predetermined byte of the ATM cell; head error control signal production means for receiving an output signal from the exclusive-OR means to produce a head error control signal; sampling. means for sampling a sample value from an output signal from the storing means; and means for processing an exclusive-OR operation with two inputs to produce the ATM cell, wherein, one of the two inputs is a sample value from the sampling means and the other is the head error control signal.